1. Field of the Invention
The present invention relates to a data transfer control unit in a computer system wherein access to data, which has already been transferred, by a CPU is possible even when all of the data has not yet been transferred without waiting for the completion of all of the data transfer.
2. Description of the Prior Art
In a computer, data transfer between an input/output unit and memory, e.g. a main memory unit, or data transfer between memory units (e.g. between a main memory unit and a cache memory), is performed by the CPU, through designation of memory areas for use in normal data transfers and for use in the aforementioned types of data transfer, with the data transfer taking place through the CPU. In this case, the CPU functions are required to implement data transfer processing, so that the CPU is unavailable for any other processing until data transfer has been completed.
With recent models of computers, a method of data transfer referred to as direct memory access (generally referred to as DMA) is becoming increasingly employed. With DMA operation, a data transfer controller executes direct transfer of data into or out of memory, without the intervention of the CPU. By utilizing a data transfer controller in this way, data can be transferred at high speed, while the CPU is made available for other processing during the process of data transfer. Thus, a DMA operation has the advantage of providing more efficient usage of the CPU.
On the other hand, when the CPU must access data which has been designated for transfer, such access cannot be executed until transfer of all data has been completed. According to the prior art, a determination as to whether or not the data required by the CPU has been transferred is carried out by software, which checks whether the transfer of all data has been completed. Furthermore, data is generally transferred in units of blocks, so that when a large amount of data is transferred it becomes necessary for the CPU to wait for a substantial time before accessing the data which it requires. This results in a low effeciency of utilization of the CPU.